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dc.contributor.authorSanyal, Sutirtha
dc.contributor.authorRoy, Sourav
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-11-07T09:01:41Z
dc.date.available2017-11-07T09:01:41Z
dc.date.issued2009
dc.identifier.citationSanyal, S., Roy, S., Cristal, A., Unsal, O., Valero, M. Clock gate on abort: Towards energy-efficient hardware transactional memory. A: IEEE International Parallel and Distributed Processing Symposium. "IPDPS 2009 Rome: proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium". Roma: Institute of Electrical and Electronics Engineers (IEEE), 2009, p. 1-8.
dc.identifier.isbn978-1-4244-3750-4
dc.identifier.urihttp://hdl.handle.net/2117/110073
dc.description.abstractTransactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a considerable amount of energy when the speculation goes wrong and transaction aborts. For Transactional Memory this wastage will typically be quite high because programmer will often mark a large portion of the code to be executed transactionally. We are proposing to turn-off a processor dynamically by gating all its clocks, whenever any transaction running in it is aborted. We have described a novel protocol which can be used in the Scalable-TCC like Hardware Transactional Memory systems. Also in the protocol we are proposing a gating-aware contention management policy to set the duration of the clock gating period precisely so that both performance and energy can be improved. With our proposal we got an average 19% savings in the total consumed energy and even an average speed-up of 4%.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors -- Programming
dc.subject.lcshParallel programming (Computer science)
dc.subject.otherHardware transactional memory
dc.subject.otherClock gating
dc.subject.otherDistributed shared memory architecture
dc.subject.otherTransaction abort
dc.subject.otherLow-power architecture
dc.titleClock gate on abort: Towards energy-efficient hardware transactional memory
dc.typeConference report
dc.subject.lemacMultiprocessadors -- Programació
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/IPDPS.2009.5160971
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5160971
dc.rights.accessOpen Access
drac.iddocument15143653
dc.description.versionPostprint (published version)
upcommons.citation.authorSanyal, S., Roy, S., Cristal, A., Unsal, O., Valero, M.
upcommons.citation.contributorIEEE International Parallel and Distributed Processing Symposium
upcommons.citation.pubplaceRoma
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIPDPS 2009 Rome: proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium
upcommons.citation.startingPage1
upcommons.citation.endingPage8


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