Clock gate on abort: Towards energy-efficient hardware transactional memory
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hdl:2117/110073
Tipus de documentText en actes de congrés
Data publicació2009
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
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Abstract
Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a considerable amount of energy when the speculation goes wrong and transaction aborts. For Transactional Memory this wastage will typically be quite high because programmer will often mark a large portion of the code to be executed transactionally. We are proposing to turn-off a processor dynamically by gating all its clocks, whenever any transaction running in it is aborted. We have described a novel protocol which can be used in the Scalable-TCC like Hardware Transactional Memory systems. Also in the protocol we are proposing a gating-aware contention management policy to set the duration of the clock gating period precisely so that both performance and energy can be improved. With our proposal we got an average 19% savings in the total consumed energy and even an average speed-up of 4%.
CitacióSanyal, S., Roy, S., Cristal, A., Unsal, O., Valero, M. Clock gate on abort: Towards energy-efficient hardware transactional memory. A: IEEE International Parallel and Distributed Processing Symposium. "IPDPS 2009 Rome: proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium". Roma: Institute of Electrical and Electronics Engineers (IEEE), 2009, p. 1-8.
ISBN978-1-4244-3750-4
Versió de l'editorhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5160971
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