Performance analysis and optimization of the FFTXlib on the Intel knights landing architecture
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
European Commission's projectMaX - Materials design at the eXascale (EC-H2020-676598)
POP - Performance Optimisation and Productivity (EC-H2020-676553)
In this paper, we address the decreasing performance of the FFTXlib, the Fast Fourier Transformation (FFT) kernel of Quantum ESPRESSO, when scaling to a full KNL node. An increased performance in the FFTXlib will likewise increase the performance of the entire Quantum ESPRESSO code one of the most used plane-wave DFT codes in the community of material science. Our approach focuses on, first, overlapping computation and communication and, second, decreasing resource contention for higher compute efficiency. In order to achieve this we use the OmpSs programming model based on task dependencies. We allow overlapping of computation and communication by converting all steps of the FFT into tasks following a flow dependency. In the same way, we decrease resource contention by converting each FFT into an individual task that can be scheduled asynchronously. In both cases, multiple FFTs can be computed in parallel. The task-based optimizations are implemented in the FFTXlib and show up to 10% runtime reduction on the already highly optimized version. Since the task scheduling is done dynamically during execution by the parallel runtime, not statically by the user, it also frees the user from finding the ideal parallel configuration himself.
CitationWagner, M., López, V., Morillo, J., Cavazzoni, C., Affinito, F., Gimenez, J., Labarta, J. Performance analysis and optimization of the FFTXlib on the Intel knights landing architecture. A: International Conference on Parallel Processing Workshops. "ICPPW 2017: 46th International Conference on Parallel Processing Workshops: 14 August 2017, Bristol, United Kingdom: proceedings". Bristol: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 243-250.