Integrating memory perspective into the BSC performance tools
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The growing gap between processor and memory speeds results in complex memory hierarchies as processors evolve to mitigate such differences by taking advantage of locality of reference. In this direction, the BSC performance analysis tools have been recently extended to provide insight relative the application memory accesses depicting their temporal and spatial characteristics, correlating with the source-code and the achieved performance simultaneously. These extensions rely on the Precise Event-Based Sampling (PEBS) mechanism available in recent Intel processors to capture information relative to the application memory accesses. The sampled information is processed with the Folding mechanism to provide a detailed temporal evolution of the memory accesses and in conjunction with the achieved performance and the source-code counterpart. The results obtained from the combination of these tools help application developers to understand better how the application behaves and how the system performs. We demonstrate the value of the complete work-flow by exploring an already optimized state-of-the-art benchmark, providing detailed insight of their memory access behavior.
CitationServat, H., Labarta, J., Hoppe, H., Gimenez, J., Peña, A. Integrating memory perspective into the BSC performance tools. A: International Conference on Parallel Processing Workshops. "ICPPW 2017: 46th International Conference on Parallel Processing Workshops: 14 August 2017, Bristol, United Kingdom: proceedings". Bristol: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 231-232.
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