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dc.contributor.authorRamirez Garcia, Tanausú
dc.contributor.authorPajuelo González, Manuel Alejandro
dc.contributor.authorSantana Jaria, Oliverio J.
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-11-06T09:06:36Z
dc.date.available2017-11-06T09:06:36Z
dc.date.issued2008
dc.identifier.citationRamirez, T., Pajuelo, M.A., Santana, O., Valero, M. Runahead threads to improve SMT performance. A: International Symposium on High-Performance Computer Architecture. "2008 IEEE 14th International Symposium on High Performance Computer Architecture". Salt Lake City, UT: Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 149-158.
dc.identifier.isbn978-1-4244-2070-4
dc.identifier.urihttp://hdl.handle.net/2117/109826
dc.description.abstractIn this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under long-latency blocking memory operations. These speculative threads prefetch data and instructions with minimal resources, reducing critical resource conflicts between threads. We compare an SMT architecture using RaT to both state-of-the-art static fetch policies and dynamic resource control policies. In terms of throughput and fairness, our results show that RaT performs better than any other policy. The proposed mechanism improves average throughput by 37% regarding previous static fetch policies and by 28% compared to previous dynamic resource scheduling mechanisms. RaT also improves fairness by 36% and 30% respectively. In addition, the proposed mechanism permits register file size reduction of up to 60% in a SMT processor without performance degradation.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshSoftware architecture
dc.subject.lcshSimultaneous multithreading processors
dc.subject.otherStorage management
dc.subject.otherMulti-threading
dc.subject.otherResource allocation
dc.titleRunahead threads to improve SMT performance
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacProgramari -- Disseny
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/HPCA.2008.4658635
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/4658635/
dc.rights.accessOpen Access
drac.iddocument21563663
dc.description.versionPostprint (published version)
upcommons.citation.authorRamirez, T., Pajuelo, M.A., Santana, O., Valero, M.
upcommons.citation.contributorInternational Symposium on High-Performance Computer Architecture
upcommons.citation.pubplaceSalt Lake City, UT
upcommons.citation.publishedtrue
upcommons.citation.publicationName2008 IEEE 14th International Symposium on High Performance Computer Architecture
upcommons.citation.startingPage149
upcommons.citation.endingPage158


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