Out-of-order vector architectures
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Register renaming and out-of-order instruction issue are now commonly used in superscalar processors. These techniques can also be used to significant advantage in vector processors, as this paper shows. Performance is improved and available memory bandwidth is used more effectively. Using a trace driven simulation we compare a conventional vector implementation, based on the Convex C3400, with an out-of-order, register renaming, vector implementation. When the number of physical registers is above 12, out-of-order execution coupled with register renaming provides a speedup of 1.24-1.72 for realistic memory latencies. Out-of-order techniques also tolerate main memory latencies of 100 cycles with a performance degradation less than 6%. The mechanisms used for register renaming and out-of-order issue can be used to support precise interrupts-generally a difficult problem in vector machines. When precise interrupts are implemented, there is typically less than a 10% degradation in performance. A new technique based on register renaming is targeted at dynamically eliminating spill code; this technique is shown to provide an extra speedup ranging between 1.10 and 1.20 while reducing total memory traffic by an average of 15-20%.
CitacióEspasa, R., Valero, M., Smith, J. Out-of-order vector architectures. A: Annual IEEE/ACM International Symposium on Microarchitecture. "Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture: December 1-3, 1997, Research Triangle Park, North Carolina: proceedings". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 160-170.
Versió de l'editorhttp://ieeexplore.ieee.org/document/645807/