Adapting cache partitioning algorithms to pseudo-LRU replacement policies
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Cita com:
hdl:2117/109404
Tipus de documentText en actes de congrés
Data publicació2010
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
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Abstract
Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least Recently Used (LRU) as the underlying replacement policy. However, it has been shown that the true LRU imposes extraordinary complexity and area overheads when implemented on high associativity caches, such as last level caches. As a consequence, current processors available on the market use pseudo-LRU replacement policies, which provide similar behavior as LRU, while reducing the hardware complexity. Thus, the presented so far LRU-based cache partitioning solutions cannot be applied to real CMP architectures. This paper proposes a complete partitioning system for caches using the pseudo-LRU replacement policy. In particular, the paper focuses on the pseudo-LRU implementations proposed by Sun Microsystems and IBM, called Not Recently Used (NRU) and Binary Tree (BT), respectively. We propose a high accuracy profiling logic and a cache partitioning hardware for both schemes. We evaluate our proposals' hardware costs in terms of area and power, and compare them against the LRU partitioning algorithm. Overall, this paper presents two hardware techniques to adapt the existing cache partitioning algorithms to real replacement policies. The results show that our solutions impose negligible performance degradation with respect to the LRU.
CitacióKedzierski, K., Moreto, M., Cazorla, F., Valero, M. Adapting cache partitioning algorithms to pseudo-LRU replacement policies. A: IEEE International Parallel and Distributed Processing Symposium. "2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)". Atlanta, Georgia: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 1-12.
ISBN978-1-4244-6441-8
Versió de l'editorhttp://ieeexplore.ieee.org/document/5470352/
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