Simulation environment for studying overlap of communication and computation
View/Open
Cita com:
hdl:2117/109231
Document typeConference report
Defense date2010
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial
property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public
communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
Overlapping communication and computation allows both processors and network to be utilized concurrently and leads to two clear benefits: overall speedup and a reduction in network performance requirements. Still, it remains unclear how much overlap can be actually achieved in practice - in real-world applications. This work designs a precise simulation environment that measures how much a scientific MPI application can profit from overlapping communication and computation. The simulation takes into account a wide range of application properties and allows to study overlap on the configurable platform. Additionally, the environment can visualize the simulated time-behaviors, so the non-overlapped and overlapped executions can be compared both quantitatively and qualitatively, providing new insights into the mechanism and potential of overlap. We found that the overlapping potential is very limited by pattern by which an application computes on the communicated data. Finally, we identified as the the biggest benefit of overlap the fact that it can highly relax network constraints without consequently degrading performance.
CitationSubotic, V., Labarta, J., Valero, M. Simulation environment for studying overlap of communication and computation. A: IEEE International Symposium on Performance Analysis of Systems and Software. "ISPASS 2010: IEEE International Symposium on Performance Analysis of Systems and Software: March 28-30, 2010, White Plains, NY, USA". Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 115-116.
ISBN978-1-4244-6022-9
Publisher versionhttp://ieeexplore.ieee.org/document/5452053/
Files | Description | Size | Format | View |
---|---|---|---|---|
05452053.pdf | 206,4Kb | View/Open |