Multithreaded vector architectures
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The purpose of this paper is to show that multi-threading techniques can be applied to a vector processor to greatly increase processor throughput and maximize resource utilization. Using a trace driven approach, we simulate a selection of the Perfect Club and Specfp92 programs and compare their execution time on a conventional vector architecture with a single memory port and on a multithreaded vector architecture. We devote an important part of this paper to study the interaction between multi-threading and main memory latency. This paper focuses on maximizing the usage of the memory port, the most expensive resource is typical vector computers. A study of the cost associated with the duplication of the vector register file is also carried out. Overall, multithreading provides for this architecture a performance advantage of more than a factor of 1.4 for realistic memory latencies, and can drive the utilization of the single memory port as high as 95%.
CitationEspasa, R., Valero, M. Multithreaded vector architectures. A: International Symposium on High-Performance Computer Architecture. "Third International Symposium on High-Performance Computer Architecture: February 1-5, 1997, San Antonio, Texas: proceedings". San Antonio, TX: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 237-248.