dc.contributor.author | Etinski, Maja |
dc.contributor.author | Corbalán González, Julita |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-10-25T09:26:29Z |
dc.date.available | 2017-10-25T09:26:29Z |
dc.date.issued | 2010 |
dc.identifier.citation | Etinski, M., Corbalán, J., Labarta, J., Valero, M. BSLD threshold driven power management policy for HPC centers. A: IEEE International Parallel and Distributed Processing Symposium. "2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)". Atlanta, Georgia: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 1-8. |
dc.identifier.isbn | 978-1-4244-6533-0 |
dc.identifier.uri | http://hdl.handle.net/2117/109117 |
dc.description.abstract | In this paper, we propose a power-aware parallel job scheduler assuming DVFS enabled clusters. A CPU frequency assignment algorithm is integrated into the well established EASY backfilling job scheduling policy. Running a job at lower frequency results in a reduction in power dissipation and accordingly in energy consumption. However, lower frequencies introduce a penalty in performance. Our frequency assignment algorithm has two adjustable parameters in order to enable fine grain energy-performance trade-off control. Furthermore, we have done an analysis of HPC system dimension. This paper investigates whether having more DVFS enabled processors for same load can lead to better energy efficiency and performance. Five workload traces from systems in production use with up to 9 216 processors are simulated to evaluate the proposed algorithm and the dimensioning problem. Our approach decreases CPU energy by 7%– 18% on average depending on allowed job performance penalty. Using the power-aware job scheduling for 20% larger system, CPU energy needed to execute same load can be decreased by almost 30% while having same or better job performance. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | High performance computing -- Energy consumption |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.other | Scheduling |
dc.subject.other | Parallel processing |
dc.subject.other | Power aware computing |
dc.title | BSLD threshold driven power management policy for HPC centers |
dc.type | Conference report |
dc.subject.lemac | Càlcul intensiu (Informàtica) -- Consum d'energia |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/IPDPSW.2010.5470913 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/5470913/ |
dc.rights.access | Open Access |
local.identifier.drac | 11152906 |
dc.description.version | Postprint (published version) |
local.citation.author | Etinski, M.; Corbalán, J.; Labarta, J.; Valero, M. |
local.citation.contributor | IEEE International Parallel and Distributed Processing Symposium |
local.citation.pubplace | Atlanta, Georgia |
local.citation.publicationName | 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) |
local.citation.startingPage | 1 |
local.citation.endingPage | 8 |