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dc.contributor.authorEtinski, Maja
dc.contributor.authorCorbalán González, Julita
dc.contributor.authorLabarta Mancho, Jesús José
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-10-25T09:26:29Z
dc.date.available2017-10-25T09:26:29Z
dc.date.issued2010
dc.identifier.citationEtinski, M., Corbalán, J., Labarta, J., Valero, M. BSLD threshold driven power management policy for HPC centers. A: IEEE International Parallel and Distributed Processing Symposium. "2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)". Atlanta, Georgia: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 1-8.
dc.identifier.isbn978-1-4244-6533-0
dc.identifier.urihttp://hdl.handle.net/2117/109117
dc.description.abstractIn this paper, we propose a power-aware parallel job scheduler assuming DVFS enabled clusters. A CPU frequency assignment algorithm is integrated into the well established EASY backfilling job scheduling policy. Running a job at lower frequency results in a reduction in power dissipation and accordingly in energy consumption. However, lower frequencies introduce a penalty in performance. Our frequency assignment algorithm has two adjustable parameters in order to enable fine grain energy-performance trade-off control. Furthermore, we have done an analysis of HPC system dimension. This paper investigates whether having more DVFS enabled processors for same load can lead to better energy efficiency and performance. Five workload traces from systems in production use with up to 9 216 processors are simulated to evaluate the proposed algorithm and the dimensioning problem. Our approach decreases CPU energy by 7%– 18% on average depending on allowed job performance penalty. Using the power-aware job scheduling for 20% larger system, CPU energy needed to execute same load can be decreased by almost 30% while having same or better job performance.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHigh performance computing -- Energy consumption
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherScheduling
dc.subject.otherParallel processing
dc.subject.otherPower aware computing
dc.titleBSLD threshold driven power management policy for HPC centers
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica) -- Consum d'energia
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/IPDPSW.2010.5470913
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/5470913/
dc.rights.accessOpen Access
local.identifier.drac11152906
dc.description.versionPostprint (published version)
local.citation.authorEtinski, M.; Corbalán, J.; Labarta, J.; Valero, M.
local.citation.contributorIEEE International Parallel and Distributed Processing Symposium
local.citation.pubplaceAtlanta, Georgia
local.citation.publicationName2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)
local.citation.startingPage1
local.citation.endingPage8


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