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The velox transactional memory stack

dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorFelber, Pascal
dc.contributor.authorRiviere, Etienne
dc.contributor.authorMoreira, Walter Maldonado
dc.contributor.authorHarmanci, Derin
dc.contributor.authorMarlier, Patrick
dc.contributor.authorDiestelhorst, Stephan
dc.contributor.authorHohmuth, Michael
dc.contributor.authorPohlack, Martin
dc.contributor.authorAfek, Yehuda
dc.contributor.authorTomić, Saša
dc.contributor.authorDrepper, Ulrich
dc.contributor.authorGramoli, Vincent
dc.contributor.authorKapalka, Michal
dc.contributor.authorGuerraoui, Rachid
dc.contributor.authorDragojevic, Aleksandar
dc.contributor.authorStenstrom, Per
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorHur, Ibrahim
dc.contributor.authorKorland, Guy
dc.contributor.authorNowack, Martin
dc.contributor.authorRiegel, Torvald
dc.contributor.authorShavit, Nir
dc.contributor.authorFetzer, Christof
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2011-01-04T13:11:17Z
dc.date.available2011-01-04T13:11:17Z
dc.date.created2010-09
dc.date.issued2010-09
dc.identifier.citationFelber, P. [et al.]. The velox transactional memory stack. "IEEE micro", Setembre 2010, vol. 30, núm. 5, p. 76-87.
dc.identifier.issn0272-1732
dc.identifier.urihttp://hdl.handle.net/2117/10906
dc.description.abstractThe transactional memory programming paradigm could become the coordination methodology of choice for actual and future multicore and many-core architectures. The transactional memory support spans a complete software and hardware stack, including programming language and hardware support, runtime and libraries, compilers, and application environments. The VELOX project has developed such a comprehensive transactional memory stack.
dc.format.extent12 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshComputer architecture
dc.subject.lcshParallel programming (Computer science)
dc.subject.lcshConcurrent programming
dc.subject.lcshVelox transactional memory stack
dc.titleThe velox transactional memory stack
dc.typeArticle
dc.subject.lemacArquitectura de computadors
dc.subject.lemacProgramació paral·lela (Informàtica)
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/MM.2010.80
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=5567088&queryText%3DThe+velox+transactional+memory+stack%26openedRefinements%3D*%26searchField%3DSearch+All
dc.rights.accessOpen Access
local.identifier.drac4464875
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/216852/EU/VELOX: An Integrated Approach to Transactional Memory on Multi- and Many-core Computers/VELOX
local.citation.authorFelber, P.; Riviere, E.; Moreira, W.; Harmanci, D.; Marlier, P.; Diestelhorst, S.; Hohmuth, M.; Pohlack, M.; Cristal, A.; Hur, I.; Unsal, O.; Stenstrom, P.; Dragojevic, A.; Guerraoui, R.; Kapalka, M.; Gramoli, V.; Drepper, U.; Tomic, S.; Afek, Y.; Korland, G.; Shavit, N.; Fetzer, C.; Nowack, M.; Riegel, T.
local.citation.publicationNameIEEE micro
local.citation.volume30
local.citation.number5
local.citation.startingPage76
local.citation.endingPage87


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