Enabling a reliable STT-MRAM main memory simulation
Tipus de documentComunicació de congrés
EditorAssociation for Computing Machinery
Condicions d'accésAccés obert
Projecte de la Comissió EuropeaExaNoDe - European Exascale Processor Memory Node Design (EC-H2020-671578)
STT-MRAM is a promising new memory technology with very desirable set of properties such as non-volatility, byte-addressability and high endurance. It has the potential to become the universal memory that could be incorporated to all levels of memory hierarchy. Although STT-MRAM technology got significant attention of various major memory manufacturers, to this day, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing parameters which are required to perform a cycle accurate main memory simulation. Our study presents a detailed analysis of STT-MRAM main memory timing and propose an approach to perform a reliable system level simulation of the memory technology. We seamlessly incorporate STT-MRAM timing parameters into DRAMSim2 memory simulator and use it as a part of the simulation infrastructure of the high-performance computing (HPC) systems. Our results suggests that, STT-MRAM main memory would provide performance comparable to DRAM, while opening up various opportunities for HPC system improvements. Most importantly, our study enables researchers to conduct reliable system level research on STT-MRAM main memory, and to explore the opportunities that this technology has to offer.
CitacióAsifuzzaman, K.; Sánchez-Verdejo, R.; Radojković, P. Enabling a reliable STT-MRAM main memory simulation. A: "MEMSYS '17 Proceedings of the International Symposium on Memory Systems". Association for Computing Machinery, 2017, p. 283-292.
Versió de l'editorhttps://dl.acm.org/citation.cfm?id=3132416