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dc.contributor.authorAcosta Ojeda, Carmelo Alexis
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.authorSantana Jaria, Oliverio J.
dc.contributor.authorFalcón Samper, Ayose Jesús
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-10-19T12:40:27Z
dc.date.available2017-10-19T12:40:27Z
dc.date.issued2009
dc.identifier.citationAcosta, C. A., Cazorla, F., Santana, O., Falcón, A., Ramírez , A., Valero, M. "Maximizing multithreaded multicore architectures through thread migrations". 2009.
dc.identifier.urihttp://hdl.handle.net/2117/108861
dc.description.abstractHeterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a complexity-effective way to expose the heterogeneity in general-purpose workloads to the underlying hardware, in order to obtain all the potential performance of these architectures. In this paper we present the Heterogeneity-Aware Dynamic Thread Migrator (hDTM), a novel complexity-effective hardware mechanism that exposes the heterogeneity in software to the hardware, also enabling the hardware to react to the dynamic behavior variations in the running applications. By means of core-to-core thread migrations, the hDTM mechanism strives to perform the desired behavior transparently to the Operating System. As an example of the general-purpose hDTM concept presented in this paper, we describe a naive hDTM implementation for a Power5-like processor and provide results on the benefits of the proposed mechanism. Our results indicate that even this simple hDTM implementation is able to get close to hDTM’s goal, not only avoiding losses due to bad thread-to-core assignments (up to a 25%) but also going beyond the best static thread-to-core assignment upper limit.
dc.format.extent16 p.
dc.language.isoeng
dc.relation.ispartofseriesUPC-DAC-RR-CAP-2009-2
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.otherMulticore
dc.subject.otherThread migration
dc.subject.otherHeterogeneity-aware
dc.titleMaximizing multithreaded multicore architectures through thread migrations
dc.typeExternal research report
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
drac.iddocument21578741
dc.description.versionPostprint (published version)
upcommons.citation.authorAcosta, C. A., Cazorla, F., Santana, O., Falcón, A., Ramírez , A., Valero, M.
upcommons.citation.publishedtrue


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