A memory model for RISC-V
Document typeConference report
PublisherBarcelona Supercomputing Center
Rights accessOpen Access
Historically memory models for multiprocessors have not been designed deliberately but have just emerged. Practically every microarchitectural optimization, which is transparent in a single threaded setting, becomes programmatically visible in a multithreaded setting. This has created a cottage industry for masochists who try to classify and understand every nuance of permitted behaviors. RISC-V offers us a unique opportunity to fix this historical wrong: specify a memory model first and make implementations conform to it. We will discuss the current proposals being debated for RISC-V memory model and point out the salient issues in this debate. These issues are atomic vs non-atomic memory systems, permitted instruction reorderings especially in the presence of dependencies, fences to control instruction reordering and ease of porting TSO programs to RISC-V. You will have a chance to express your opinions which I will report to the committee.
CitationArvind. A memory model for RISC-V. A: 3rd Severo Ochoa Research Seminar Lectures at BSC, Barcelona, 2016-2017. "Book of abstracts". Barcelona: Barcelona Supercomputing Center, 2017, p. 51-52.