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dc.contributor.authorRigo, Alvise
dc.contributor.authorPinto, Christian
dc.contributor.authorPouget, Kevin
dc.contributor.authorRaho, Daniel
dc.contributor.authorDutoit, Denis
dc.contributor.authorMartinez, Pierre-Yves
dc.contributor.authorDoran, Chris
dc.contributor.authorBenini, Luca
dc.contributor.authorMavroidis, Iakovos
dc.contributor.authorMarazakis, Manolis
dc.contributor.authorBartsch, Valeria
dc.contributor.authorLonsdale, Guy
dc.contributor.authorPop, Antoniu
dc.contributor.authorGoodacre, John
dc.contributor.authorColliot, Annaïk
dc.contributor.authorCarpenter, Paul
dc.contributor.authorRadojkovic, Petar
dc.contributor.authorPleiter, Dirk
dc.contributor.authorDrouin, Dominique
dc.contributor.authorDupont de Dinechin, Benoît
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2017-10-17T10:11:36Z
dc.date.available2017-10-17T10:11:36Z
dc.date.issued2017-09-28
dc.identifier.citationRigo, A. [et al.]. Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach. A: "Digital System Design (DSD), 2017 Euromicro Conference on". IEEE, 2017, p. 486-493.
dc.identifier.isbn978-1-5386-2146-2
dc.identifier.urihttp://hdl.handle.net/2117/108741
dc.description.abstractPower consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed in order to cope with the requirements of this forthcoming computing target. This paper presents the ExaNoDe H2020 research project aiming to design a highly energy efficient and highly integrated heterogeneous compute node targeting Exascale level computing, mixing low-power processors, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system.
dc.description.sponsorshipThis work was supported by the ExaNoDe project that has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 671578. The work presented in this paper reflects only authors’ view and the European Commission is not responsible for any use that may be made of the information it contains.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherIEEE
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshHigh performance computing
dc.subject.lcshComputer architecture
dc.subject.otherPower demand
dc.subject.otherSupercomputers
dc.subject.otherSilicon
dc.subject.otherHardware
dc.subject.otherProgram processors
dc.subject.otherComputational modeling
dc.subject.otherComputer architecture
dc.subject.otherExascale
dc.subject.otherHPC
dc.subject.otherUnimem
dc.subject.otherSilicon interposer
dc.subject.otherVirtualization
dc.titlePaving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach
dc.typeConference lecture
dc.subject.lemacSupercomputadors
dc.subject.lemacProgramari--Disseny
dc.identifier.doi10.1109/DSD.2017.37
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/8049829/
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/671578/EU/European Exascale Processor Memory Node Design/ExaNoDe
local.citation.publicationNameDigital System Design (DSD), 2017 Euromicro Conference on
local.citation.startingPage486
local.citation.endingPage493


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Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain