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dc.contributor.authorQuintana Rodríguez, Francisca
dc.contributor.authorEspasa Sans, Roger
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-10-06T09:10:40Z
dc.date.available2017-10-06T09:10:40Z
dc.date.issued1998
dc.identifier.citationQuintana, F., Espasa, R., Valero, M. A case for merging the ILP and DLP paradigms. A: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. "Proceedings of the 6th EUROMICRO Workshop on Parallel and Distributed Processing, PDP'98: University of Madrid: January 21-23, 1998, Madrid, Spain". Madrid: Institute of Electrical and Electronics Engineers (IEEE), 1998, p. 217-224.
dc.identifier.isbn0-8186-8332-5
dc.identifier.urihttp://hdl.handle.net/2117/108433
dc.description.abstractThe goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved using either paradigm on its own. We will show that the combination of the two techniques yields very high performance at a low cost and a low complexity. We will show that this architecture can reach a performance equivalent to a superscalar processor that sustained 10 instructions per cycle. We will see that the machine exploiting both types of parallelism improves upon the ILP-only machine by factors of 1.5-1.8. We also present a study on the scalability of both paradigms and show that, when we increase resources to reach a 16-issue machine, the advantage of the ILP+DLP machine over the ILP-only machine increases up to 2.0-3.45. While the peak achieved IPC for the ILP machine is 4, the ILP+DLP machine exceeds 10 instructions per cycle.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshComputational complexity
dc.subject.otherPerformance evaluation
dc.subject.otherParallel architectures
dc.titleA case for merging the ILP and DLP paradigms
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacComplexitat computacional
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/EMPDP.1998.647201
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/647201/
dc.rights.accessOpen Access
drac.iddocument2420697
dc.description.versionPostprint (published version)
upcommons.citation.authorQuintana, F.; Espasa, R.; Valero, M.
upcommons.citation.contributorEuromicro International Conference on Parallel, Distributed, and Network-Based Processing
upcommons.citation.pubplaceMadrid
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 6th EUROMICRO Workshop on Parallel and Distributed Processing, PDP'98: University of Madrid: January 21-23, 1998, Madrid, Spain
upcommons.citation.startingPage217
upcommons.citation.endingPage224


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