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A case for merging the ILP and DLP paradigms

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10.1109/EMPDP.1998.647201
 
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hdl:2117/108433

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Quintana Rodríguez, Francisca
Espasa Sans, RogerMés informacióMés informació
Valero Cortés, MateoMés informacióMés informacióMés informació
Document typeConference report
Defense date1998
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved using either paradigm on its own. We will show that the combination of the two techniques yields very high performance at a low cost and a low complexity. We will show that this architecture can reach a performance equivalent to a superscalar processor that sustained 10 instructions per cycle. We will see that the machine exploiting both types of parallelism improves upon the ILP-only machine by factors of 1.5-1.8. We also present a study on the scalability of both paradigms and show that, when we increase resources to reach a 16-issue machine, the advantage of the ILP+DLP machine over the ILP-only machine increases up to 2.0-3.45. While the peak achieved IPC for the ILP machine is 4, the ILP+DLP machine exceeds 10 instructions per cycle.
CitationQuintana, F., Espasa, R., Valero, M. A case for merging the ILP and DLP paradigms. A: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. "Proceedings of the 6th EUROMICRO Workshop on Parallel and Distributed Processing, PDP'98: University of Madrid: January 21-23, 1998, Madrid, Spain". Madrid: Institute of Electrical and Electronics Engineers (IEEE), 1998, p. 217-224. 
URIhttp://hdl.handle.net/2117/108433
DOI10.1109/EMPDP.1998.647201
ISBN0-8186-8332-5
Publisher versionhttp://ieeexplore.ieee.org/document/647201/
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  • CAP - Grup de Computació d'Altes Prestacions - Ponències/Comunicacions de congressos [779]
  • Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.827]
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