Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Shows that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a performance level that cannot be achieved using either paradigm on its own. We show that the combination of the two techniques yields very high performance at a low cost and a low complexity. We show that this architecture achieves a sustained performance on numerical regular codes that is 20 times the performance that can be achieved with today's superscalar microprocessors. Moreover, we show that the architecture can tolerate very large memory latencies, of up to a 100 cycles, with a relatively small performance degradation. This high performance is independent of working set size or of locality considerations, since the DLP paradigm allows very efficient exploitation of a high-performance flat memory bandwidth.
CitationEspasa, R., Valero, M. Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. A: International Conference on High-Performance Computing. "Fourth International Conference on High-Performance Computing: December 18-21, 1997, Bangalore, India: proceedings". Bangalore: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 350-357.