Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis
Document typeConference lecture
Rights accessOpen Access
Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not been demonstrated yet. In this paper, in the context of probabilistic timing analysis (PTA), we propose a PTA-compatible wNoC design that provides tight time-composable contention bounds. The proposed wNoC design builds on PTA ability to reason in probabilistic terms about hardware events impacting execution time (e.g. wNoC contention), discarding those sequences of events occurring with a negligible low probability. This allows our wNoC design to deliver improved guaranteed performance. ur results show that WCET estimates of applications running on top of probabilistic wNoCs are reduced by 40% and 75% on average for 4x4 and 6x6 wNoC setups respectively when compared against deterministic wNoCs.
CitationSlijepcevic, M. [et al.]. Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis. A: "2017 Euromicro Conference on Digital System Design (DSD)". IEEE, 2017, p. 440-444.