Fast speculative address generation and way caching for reducing L1 data cache energy
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access latency can be affected as well, leading to an increase in overall energy consumption due to increased execution time. At the same time, the static energy consumption of the cache increases significantly with each new process generation. This paper proposes a new approach to reduce the overall L1 cache energy consumption using a combination of way caching and fast, speculative address generation. A 16-entry way cache storing a 3-bit way number for recently accessed L1 data cache lines is shown sufficient to significantly reduce both static and dynamic energy consumption of the L1 cache. Fast speculative address generation helps to hide the way cache access latency and is highly accurate. The L1 cache energy-delay product is reduced by 10% compared to using the way cache alone and by 37% compared to the use of multiple MRU technique.
CitacióNicolaescu, D., Salamat, B., Veidenbaum, A., Valero, M. Fast speculative address generation and way caching for reducing L1 data cache energy. A: IEEE International Conference on Computer Design. "2006 International Conference on Computer Design". San Jose, CA: Institute of Electrical and Electronics Engineers (IEEE), 2006, p. 101-107.
Versió de l'editorhttp://ieeexplore.ieee.org/document/4380801/