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dc.contributor.authorArumi Delgado, Daniel
dc.contributor.authorRodríguez Montañés, Rosa
dc.contributor.authorManich Bou, Salvador
dc.contributor.authorPehl, Michael
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.identifier.citationArumi, D., Rodriguez-Montanes, R., Manich, S., Pehl, M. RRAM Based Random Bit Generation for Hardware Security Applications. A: Conference on Design of Circuits and Integrated Systems. "Proceedings: 2016 Conference on Design of Circuits and Integrated Systems: DCIS 2016: November 23rd-25th 2016, Granada, Spain". Granada: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-6.
dc.description© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractResistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. The stochastic switching mechanism and intrinsic variability of RRAMs still poses challenges that must be overcome prior to their massive memory commercialization. However, these very same features open a wide range of potential applications for these devices in hardware security. In this context, this work proposes the generation of a random bit by means of simultaneous write operation of two parallel cells so that only one of them unpredictably switches its state. Electrical simulations confirm the strong stochastic behavior and stability of the proposed primitive. Exploiting this fact, a Physical Unclonable Function (PUF) like primitive is implemented based on modified 1 transistor - 1 resistor (1T1R) array structure.
dc.format.extent6 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshIntegrated circuits
dc.subject.lcshStochastic systems
dc.subject.othermemory array
dc.subject.otherstochastic switching
dc.subject.otherhardware security
dc.titleRRAM Based Random Bit Generation for Hardware Security Applications
dc.typeConference report
dc.subject.lemacCircuits integrats
dc.subject.lemacSistemes estocàstics
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
local.citation.authorArumi, D.; Rodriguez-Montanes, R.; Manich, S.; Pehl, M.
local.citation.contributorConference on Design of Circuits and Integrated Systems
local.citation.publicationNameProceedings: 2016 Conference on Design of Circuits and Integrated Systems: DCIS 2016: November 23rd-25th 2016, Granada, Spain

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