ROB-free architecture proposal
Document typeExternal research report
Rights accessOpen Access
Modern processors improve performance by taking advantage of the instruction level parallelism (ILP) by means of allowing hundreds of instructions in flight. However, they still have to face an important source of degradation coming from the increasing difference between the processor and the main memory speeds (memory wall). In order to overcome this problem, recent proposals allow even more instructions in flight by replacing a re-order buffer (ROB) with a checkpointing mechanism and an out-of-order retirement of the processors resources, relaxing other desirable features like the precise recovery of the state on mispredicted branches or exceptions, possibly re-executing correct-path instructions on a recovery.
This Technical Report was sent to Advisory Committee of MICRO-40 (June 8th, 2007) for review and published in the Spanish Workshop on Parallelism on September 2006 and September 2007. Outstanding Technical Report: UPC-DAC-2002-43 (September 6th, 2002) 'Large virtual ROBs by processor checkpointing'
CitationGonzález, I., Galluzzi, M., Cristal, A., Pajuelo, M.A., Santana, O., Valero, M. "ROB-free architecture proposal". 2007.
Is part ofUPC-DAC-RR-CAP-2007-25