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dc.contributor.authorWagner, Michael
dc.contributor.authorGimenez, Judit
dc.date.accessioned2017-09-26T08:37:35Z
dc.date.available2017-09-26T08:37:35Z
dc.date.issued2017-05-04
dc.identifier.citationWagner, M.; Gimenez, J. Performance analysis on the Intel Knights Landing architecture. A: BSC Severo Ochoa International Doctoral Symposium (4th: 2017: Barcelona). "Book of abstracts". Barcelona: Barcelona Supercomputing Center, 2017, p. 66.
dc.identifier.urihttp://hdl.handle.net/2117/107993
dc.description.abstractOne of the emerging architectures in HPC systems is Intel’s Knights Landing (KNL) many core chip, which will also be part of BSC’s next HPC installation MareNostrum 4. KNL is the code name of the second generation of Intel XEON Phi, a many integrated core architecture (MIC) with up to 72 cores with four-time hyper-threading. It includes up to 384 GB of DDR4 RAM and 8-16 GB of stacked MCDRAM, a version of high bandwidth memory. In addition, each core will have two 512-bit vector units and will support AVX-512 SIMD instructions.
dc.format.extent1 p.
dc.language.isoeng
dc.publisherBarcelona Supercomputing Center
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHigh performance computing
dc.subject.otherHPC
dc.subject.otherPerformance analysis
dc.subject.otherPerformance optimization
dc.subject.otherTools
dc.subject.otherIntel Knights Landing
dc.titlePerformance analysis on the Intel Knights Landing architecture
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.rights.accessOpen Access
local.citation.contributorBSC Severo Ochoa International Doctoral Symposium (4th: 2017: Barcelona)
local.citation.pubplaceBarcelona
local.citation.publicationNameBook of abstracts
local.citation.startingPage66
local.citation.endingPage66


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