Modelling bus contention during system early design stages
Document typeConference lecture
Rights accessOpen Access
Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early stages applications are not yet consolidated and IP constraints may prevent sharing them across providers, challenging the estimation of contention bounds. In this paper, we propose a model to estimate the increase in applications' execution time due to on-chip bus sharing when they simultaneously execute in a multicore. The model works with information derived from the execution of each application in isolation, hence, without the need to actually run applications simultaneously. The model improves inaccuracy with respect to the existing model, and tends to over-estimate. The latter, is very important to prevent that, during late design stages, applications miss their deadline when consolidated into the same multicore, causing costly system redesign.
CitationTrilla, D. [et al.]. Modelling bus contention during system early design stages. A: "2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)". IEEE, 2017, p. 1-8.