Runtime-assisted shared cache insertion policies based on re-reference intervals
Document typeConference report
Rights accessOpen Access
European Commission's projectROMOL - Riding on Moore's Law (EC-FP7-321253)
Processor speed is improving at a faster rate than the speed of main memory, which makes memory accesses increasingly expensive. One way to solve this problem is to reduce miss ratio of the processor’s last level cache by improving its replacement policy. We approach the problem by co-designing the runtime system and hardware and exploiting the semantics of the applications written in data-flow task-based programming models to provide hardware with information about the task types and task data-dependencies. We propose the Task-Type aware Insertion Policy, TTIP, which uses the runtime system to dynamically determine the best probability per task type for bimodal insertion in the recency stack and the static Dependency-Type aware Insertion Policy, DTIP, that inserts cache lines in the optimal position taking into account the dependency types of the current task. TTIP and DTIP perform similarly or better than state-of-the-art replacement policies, while requiring less hardware.
CitationDimic, V., Moreto, M., Casas, M., Valero, M. Runtime-assisted shared cache insertion policies based on re-reference intervals. A: International European Conference on Parallel and Distributed Computing. "Euro-Par 2017: Parallel Processing: 23rd International Conference on Parallel and Distributed Computing: Santiago de Compostela, Spain, August 28-September 1, 2017: proceedings". Santiago de Compostela: Springer, 2017, p. 247-259.
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