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dc.contributor.authorKnijnenburg, Peter M.W.
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorLatorre Salinas, Fernando
dc.contributor.authorLarriba Pey, Josep
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-09-15T09:02:07Z
dc.date.available2017-09-15T09:02:07Z
dc.date.issued2002
dc.identifier.citationKnijnenburg, P., Ramírez, A., Latorre, F., Larriba, J., Valero, M. Branch classification to control instruction fetch in simultaneous multithreaded architectures. A: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. "International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems". Big Island, HI: Institute of Electrical and Electronics Engineers (IEEE), 2002, p. 67-76.
dc.identifier.isbn0-7695-1635-1
dc.identifier.urihttp://hdl.handle.net/2117/107650
dc.description.abstractIn simultaneous multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that threads are competing for resources and in many cases this competition can actually degrade overall performance. There are two major causes for this: first, instructions that, because of a long latency data cache miss, cause dependent instructions not to proceed for many cycles thereby wasting space in the instruction queues, and second, execution of instructions that belong to a mispredicted path. Both of these have a harmful effect on throughput and the second moreover wastes energy. in this paper we propose a fetch policy that avoids issuing instructions to the pipeline if we are not confident that the instruction belongs to the correct execution path. In this way, we avoid using resources for instructions that will not contribute to performance. This fetch policy, called agstall, is based on a dynamic branch classification mechanism. Branch instances are classified as either strongly biased or not strongly biased. We consider all strongly biased branches as easy to predict, and we stall the thread on branches that are not strongly biased to avoid mispredicting them. Our results show that agstall achieves similar or better performance than icount, and reduces by up to 86% the number of wrong-path instructions executed.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCache memory
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherParallel architectures
dc.subject.otherMulti-threading
dc.subject.otherCache storage
dc.titleBranch classification to control instruction fetch in simultaneous multithreaded architectures
dc.typeConference report
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/IWIA.2002.1035020
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1035020/
dc.rights.accessOpen Access
drac.iddocument2345581
dc.description.versionPostprint (published version)
upcommons.citation.authorKnijnenburg, P., Ramírez, A., Latorre, F., Larriba, J., Valero, M.
upcommons.citation.contributorInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
upcommons.citation.pubplaceBig Island, HI
upcommons.citation.publishedtrue
upcommons.citation.publicationNameInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
upcommons.citation.startingPage67
upcommons.citation.endingPage76


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