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Latency tolerant branch predictors
dc.contributor.author | Santana Jaria, Oliverio J. |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-09-14T11:34:38Z |
dc.date.available | 2017-09-14T11:34:38Z |
dc.date.issued | 2003 |
dc.identifier.citation | Santana, O., Ramírez , A., Valero, M. Latency tolerant branch predictors. A: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. "Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems". Maui, Hawaii: IEEE Press, 2003, p. 30-39. |
dc.identifier.isbn | 0-7695-2019-7 |
dc.identifier.uri | http://hdl.handle.net/2117/107625 |
dc.description.abstract | The access latency of branch predictors is a well known problem of fetch engine design. Prediction overriding techniques are commonly accepted to overcome this problem. However, prediction overriding requires a complex recovery mechanism to discard the wrong speculative work based on overridden predictions. In this paper, we show that stream and trace predictors, which use long basic prediction units, can tolerate access latency without needing overriding, thus reducing fetch engine complexity. We show that both the stream fetch engine and the trace cache architecture not using overriding outperform other efficient fetch engines, such as an EV8-like fetch architecture or the FTB fetch engine, even when they do use overriding. |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.publisher | IEEE Press |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Compilers (Computer programs) |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.other | Parallel architectures |
dc.subject.other | Cache storage |
dc.subject.other | System recovery |
dc.subject.other | Instruction sets |
dc.subject.other | Program compilers |
dc.title | Latency tolerant branch predictors |
dc.type | Conference report |
dc.subject.lemac | Compiladors (Programes d'ordinador) |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/IWIA.2003.1262780 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1262780/ |
dc.rights.access | Open Access |
local.identifier.drac | 21543190 |
dc.description.version | Postprint (published version) |
local.citation.author | Santana, O.; Ramírez, A.; Valero, M. |
local.citation.contributor | International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems |
local.citation.pubplace | Maui, Hawaii |
local.citation.publicationName | Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems |
local.citation.startingPage | 30 |
local.citation.endingPage | 39 |