Latency tolerant branch predictors
Tipo de documentoTexto en actas de congreso
Fecha de publicación2003
Condiciones de accesoAcceso abierto
The access latency of branch predictors is a well known problem of fetch engine design. Prediction overriding techniques are commonly accepted to overcome this problem. However, prediction overriding requires a complex recovery mechanism to discard the wrong speculative work based on overridden predictions. In this paper, we show that stream and trace predictors, which use long basic prediction units, can tolerate access latency without needing overriding, thus reducing fetch engine complexity. We show that both the stream fetch engine and the trace cache architecture not using overriding outperform other efficient fetch engines, such as an EV8-like fetch architecture or the FTB fetch engine, even when they do use overriding.
CitaciónSantana, O., Ramírez , A., Valero, M. Latency tolerant branch predictors. A: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. "Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems". Maui, Hawaii: IEEE Press, 2003, p. 30-39.
Versión del editorhttp://ieeexplore.ieee.org/document/1262780/