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Transistor count and chip-space estimation of simplescalar-based microprocessor model
dc.contributor.author | Steinhaus, Marc |
dc.contributor.author | Kolla, Reiner |
dc.contributor.author | Larriba Pey, Josep |
dc.contributor.author | Ungerer, Theo |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-09-08T10:05:18Z |
dc.date.available | 2017-09-08T10:05:18Z |
dc.date.issued | 2001 |
dc.identifier.citation | Steinhaus, M., Kolla, R., Larriba, J., Ungerer, T., Valero, M. Transistor count and chip-space estimation of simplescalar-based microprocessor model. A: Workshop on Complexity-Effective Design. "Workshop on Complexity-Effective Design: June 30, 2001 Goteborg, Sweden". Goteborg: 2001, p. 1-15. |
dc.identifier.uri | http://hdl.handle.net/2117/107519 |
dc.description.abstract | This paper proposes a chip space and transistor count estimation tool, which receives its input from the baseline architecture and the configuration file of the microarchitecture performance simulator sim-outorder of the SimpleScalar Tool Set. The estimation tool yields a pre-silicon chip space and transistor count estimation and allows to compare different microprocessor configurations with respect to their potential chip space requirements. The estimation method, which is the basis of our tool, is validated by configuration parameters of a real processor yielding a transistor count and a chip space estimation that is very close to the real processor numbers. |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Microprocessors -- Design and construction |
dc.subject.other | Transistor count |
dc.subject.other | Chip-space estimation |
dc.subject.other | Simplescalar-based microprocessor model |
dc.title | Transistor count and chip-space estimation of simplescalar-based microprocessor model |
dc.type | Conference report |
dc.subject.lemac | Microprocessadors -- Disseny i construcció |
dc.contributor.group | Universitat Politècnica de Catalunya. DAMA-UPC - Data Management Group |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.rights.access | Open Access |
local.identifier.drac | 21478695 |
dc.description.version | Postprint (author's final draft) |
local.citation.author | Steinhaus, M.; Kolla, R.; Larriba, J.; Ungerer, T.; Valero, M. |
local.citation.contributor | Workshop on Complexity-Effective Design |
local.citation.pubplace | Goteborg |
local.citation.publicationName | Workshop on Complexity-Effective Design: June 30, 2001 Goteborg, Sweden |
local.citation.startingPage | 1 |
local.citation.endingPage | 15 |