Design and implementation of ultra-high speed automatic flexible controlled SOA equalizer with wide dynamic range
Tipus de documentProjecte Final de Màster Oficial
Condicions d'accésAccés obert
The research work described in this thesis focuses on the design, implementation and measurement of an analog ultra-high speed Semicondutor Optical Ampliffier (SOA) equalizer. These activities are carried out in the framework of Erasmus+ internship program. Introducing optical switching technology, it has a prospective of offering exibility, power efficiency, providing large capacity and fast response. In this thesis, the resolution of monitoring and equalization of the power for these fast optical switches is studied. Not controlling the optical power, consecutive packets may suffer large variations in the signal power level. In an optical packet switching scenario, the dynamic performance of the packets duration is so short that analog circuit has to respond with enough speed to equalize the packets in this range of time. A fast optical switch usually use semiconductor optical amplifier (SOA) as switching gates, so their utility to equalize power variation of the packets becomes increasingly attractive due to its fast nano-scale response and adjustable optical gain. The analog equalizer has to provide the correct bias current to an in-line SOA for an equal- ization of the packets in a specific sub-micron time response. This is accomplished by studying the mathematical concept of equalization up to fully design an analog circuit. Simulation of each stage as well as the whole circuit performance has been employed, showing promising results in the dynamics of the circuit, 100 ns response time. Moreover, the design of a Printed Circuit Board (PCB) layout to integrate different prototypes has also been exploited, where two prototypes has been presented: fixed-slope configuration (High-Speed Equalizer v1.0) and full- exible configura- tion (High-Speed Equalizer 2.0). In the second prototype, programmable functionalities improving the exibility of the equalizer can be supported, by updating the value of the slope and reference voltage of the scaling stage in 68 ms. Exploiting the capability of the prototype, two different regions has been tested, achieving a linear dynamic range of 10dB. Finally, a response time of 150 ns is reached by the full- exible configuration with an average power consumption of 1.3W, where the penalty is introduced by the digital potentiometers.