Mostra el registre d'ítem simple

dc.contributor.authorVourkas, Ioannis
dc.contributor.authorGomez, Jorge
dc.contributor.authorAbusleme, Angel
dc.contributor.authorVasileiadis, Nikolaos
dc.contributor.authorSirakoulis, Georgios
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2017-07-28T11:17:58Z
dc.date.issued2017
dc.identifier.citationVourkas, I., Gomez, J., Abusleme, A., Vasileiadis, N., Sirakoulis, G., Rubio, A. Exploring the voltage divider approach for accurate memristor state tuning. A: Latin American Symposium on Circuits and Systems. "2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS 2017): Bariloche, Argentina: 20-23 February 2017". Bariloche: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-4.
dc.identifier.isbn978-1-5090-5859-4
dc.identifier.urihttp://hdl.handle.net/2117/107035
dc.description.abstractThe maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multilevel programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve <1% tuning precision, on average 3× faster than another accurate tuning algorithm of the recent literature.
dc.format.extent4 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria elèctrica::Maquinària i aparells elèctrics
dc.subject.lcshCircuits elèctrics
dc.subject.otherMemristor
dc.subject.otherResistive switching
dc.subject.otherResistive RAM
dc.subject.otherTuning
dc.subject.otherVoltage divider
dc.subject.otherMulti-level storage
dc.titleExploring the voltage divider approach for accurate memristor state tuning
dc.typeConference report
dc.subject.lemacElectric circuits
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/LASCAS.2017.7948043
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/7948043/
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac21209938
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TEC2013-45638-C3-2-R/ES/APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES/
dc.date.lift10000-01-01
local.citation.authorVourkas, I.; Gomez, J.; Abusleme, A.; Vasileiadis, N.; Sirakoulis, G.; Rubio, A.
local.citation.contributorLatin American Symposium on Circuits and Systems
local.citation.pubplaceBariloche
local.citation.publicationName2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS 2017): Bariloche, Argentina: 20-23 February 2017
local.citation.startingPage1
local.citation.endingPage4


Fitxers d'aquest items

Imatge en miniatura

Aquest ítem apareix a les col·leccions següents

Mostra el registre d'ítem simple