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Statistical characterization and modeling of random telegraph noise effects in 65nm SRAM cells

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10.1109/SMACD.2017.7981610
 
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hdl:2117/107030

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Martinez, Javier
Rodriguez, Rosa
Nafría Maqueda, MontserratMés informació
Torrents, Gabriel
Bota, Sebastian A .
Segura, Jaume
Moll Echeto, Francisco de BorjaMés informacióMés informacióMés informació
Rubio Sola, Jose AntonioMés informacióMés informacióMés informació
Document typeConference report
Defense date2017
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
ProjectAPROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES (MINECO-TEC2013-45638-C3-2-R)
Abstract
Random Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is derived by applying statistical and physics based Montecarlo modeling to the experimental data. Results show that RTN can have a significant impact on the memory write operations and should therefore be taken into account during the memory design phase
CitationMartinez, J., Rodriguez, R., Nafria, M., Torrents, G., Bota, S.A., Segura, J., Moll, F., Rubio, A. Statistical characterization and modeling of random telegraph noise effects in 65nm SRAM cells. A: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. "SMACD 2017: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design: 12th-15th June 2017: Giardini Naxos, Taormina, Itlaly". Giardini Naxos, Taormina: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-4. 
URIhttp://hdl.handle.net/2117/107030
DOI10.1109/SMACD.2017.7981610
ISBN978-1-5090-5052-9
Publisher versionhttp://ieeexplore.ieee.org/abstract/document/7981610/
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  • HIPICS - High Performance Integrated Circuits and Systems - Ponències/Comunicacions de congressos [144]
  • Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos [1.643]
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