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dc.contributor.authorSerrano, Maria A.
dc.contributor.authorMelani, Alessandra
dc.contributor.authorKehr, Sebastian
dc.contributor.authorBertogna, Marko
dc.contributor.authorQuiñones, Eduardo
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2017-07-28T09:05:29Z
dc.date.available2017-07-28T09:05:29Z
dc.date.issued2017-07-03
dc.identifier.citationSerrano, M. A. [et al.]. An Analysis of Lazy and Eager Limited Preemption Approaches under DAG-Based Global Fixed Priority Scheduling. A: "2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC)". Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 193-202.
dc.identifier.isbn978-1-5386-1574-4
dc.identifier.urihttp://hdl.handle.net/2117/107002
dc.description.abstractDAG-based scheduling models have been shown to effectively express the parallel execution of current many-core heterogeneous architectures. However, their applicability to real-time settings is limited by the difficulties to find tight estimations of the worst-case timing parameters of tasks that may arbitrarily be preempted/migrated at any instruction. An efficient approach to increase the system predictability is to limit task preemptions to a set of pre-defined points. This limited preemption model supports two different preemption approaches, eager and lazy, which have been analyzed only for sequential task-sets. This paper proposes a new response time analysis that computes an upper bound on the lower priority blocking that each task may incur with eager and lazy preemptions. We evaluate our analysis with both, synthetic DAG-based task-sets and a real case-study from the automotive domain. Results from the analysis demonstrate that, despite the eager approach generates a higher number of priority inversions, the blocking impact is generally smaller than in the lazy approach, leading to a better schedulability performance.
dc.description.sponsorshipThis work was funded by the EU projects P-SOCRATES (FP7-ICT-2013-10) and HERCULES (H2020/ICT/2015/688860), and the Spanish Ministry of Science and Innovation under contract TIN2015-65316-P.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria elèctrica
dc.subject.lcshComputers--Research
dc.subject.lcshParallel programming (Computer science)
dc.subject.otherComputational modeling
dc.subject.otherInterference
dc.subject.otherReal-time systems
dc.subject.otherProcessor scheduling
dc.subject.otherComputer architecture
dc.subject.otherAnalytical models
dc.subject.otherParallel programming
dc.titleAn Analysis of Lazy and Eager Limited Preemption Approaches under DAG-Based Global Fixed Priority Scheduling
dc.typeConference lecture
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacOrdinadors--Dispositius de memòria
dc.identifier.doi10.1109/ISORC.2017.9
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/7964887/
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/688860/EU/High-Performance Real-time Architectures for Low-Power Embedded Systems/HERCULES
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2015-65316-P
local.citation.publicationName2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC)
local.citation.startingPage193
local.citation.endingPage202


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