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dc.contributor.authorGaydadjiev, Georgi
dc.contributor.authorIsaza, Sebastian
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorCabarcas, Felipe
dc.contributor.authorJuurlink, Ben
dc.contributor.authorÁlvarez Mesa, Mauricio
dc.contributor.authorSánchez Castaño, Friman
dc.contributor.authorAzevedo, Arnaldo
dc.contributor.authorMeenderinck, Cor
dc.contributor.authorCiobanu, Catalin
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-12-20T16:21:01Z
dc.date.available2010-12-20T16:21:01Z
dc.date.created2010-10
dc.date.issued2010-10
dc.identifier.citationRamirez, A. [et al.]. The SARC architecture. "IEEE micro", Octubre 2010, vol. 30, núm. 5, p. 16-29.
dc.identifier.issn0272-1732
dc.identifier.urihttp://hdl.handle.net/2117/10688
dc.description.abstractThe SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.
dc.format.extent14 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHeterogeneous computing
dc.subject.otherMulticore
dc.subject.otherHeterogeneous architecture
dc.subject.otherAccelerator
dc.subject.otherProgramming model
dc.titleThe SARC architecture
dc.typeArticle
dc.subject.lemacArquitectura d'ordinadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
drac.iddocument4465089
dc.description.versionPostprint (published version)
upcommons.citation.authorRamirez, A.; Cabarcas, F.; Juurlink, B.; Alvarez, M.; Sanchez, F.; Azevedo, A.; Meenderinck, C.; Ciobanu, C.; Isaza, S.; Gaydadjiev, G.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE micro
upcommons.citation.volume30
upcommons.citation.number5
upcommons.citation.startingPage16
upcommons.citation.endingPage29


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