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The SARC architecture
| dc.contributor.author | Gaydadjiev, Georgi |
| dc.contributor.author | Isaza, Sebastian |
| dc.contributor.author | Ramírez Bellido, Alejandro |
| dc.contributor.author | Cabarcas, Felipe |
| dc.contributor.author | Juurlink, Ben |
| dc.contributor.author | Álvarez Mesa, Mauricio |
| dc.contributor.author | Sánchez Castaño, Friman |
| dc.contributor.author | Azevedo, Arnaldo |
| dc.contributor.author | Meenderinck, Cor |
| dc.contributor.author | Ciobanu, Catalin |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2010-12-20T16:21:01Z |
| dc.date.available | 2010-12-20T16:21:01Z |
| dc.date.created | 2010-10 |
| dc.date.issued | 2010-10 |
| dc.identifier.citation | Ramirez, A. [et al.]. The SARC architecture. "IEEE micro", Octubre 2010, vol. 30, núm. 5, p. 16-29. |
| dc.identifier.issn | 0272-1732 |
| dc.identifier.uri | http://hdl.handle.net/2117/10688 |
| dc.description.abstract | The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors. |
| dc.format.extent | 14 p. |
| dc.language.iso | eng |
| dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Heterogeneous computing |
| dc.subject.other | Multicore |
| dc.subject.other | Heterogeneous architecture |
| dc.subject.other | Accelerator |
| dc.subject.other | Programming model |
| dc.title | The SARC architecture |
| dc.type | Article |
| dc.subject.lemac | Arquitectura d'ordinadors |
| dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| dc.rights.access | Open Access |
| local.identifier.drac | 4465089 |
| dc.description.version | Postprint (published version) |
| local.citation.author | Ramirez, A.; Cabarcas, F.; Juurlink, B.; Alvarez, M.; Sanchez, F.; Azevedo, A.; Meenderinck, C.; Ciobanu, C.; Isaza, S.; Gaydadjiev, G. |
| local.citation.publicationName | IEEE micro |
| local.citation.volume | 30 |
| local.citation.number | 5 |
| local.citation.startingPage | 16 |
| local.citation.endingPage | 29 |
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