Show simple item record

dc.contributor.authorRadojkovic, Petar
dc.contributor.authorCakarevic, Vladimir
dc.contributor.authorVerdú Mulà, Javier
dc.contributor.authorPajuelo González, Manuel Alejandro
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.authorNemirovsky, Mario
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-12-20T12:35:32Z
dc.date.available2010-12-20T12:35:32Z
dc.date.created2010-05
dc.date.issued2010-05
dc.identifier.citationRadojkovic, P. [et al.]. Thread to strand binding of parallel network applications in massive multi-threaded systems. "ACM SIGPLAN notices", Maig 2010, vol. 45, núm. 5, p. 191-201.
dc.identifier.issn0362-1340
dc.identifier.urihttp://hdl.handle.net/2117/10681
dc.description.abstractIn processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT or pure-CMP processors. Once the operating system selects the set of applications to simultaneously schedule on the processor (workload), each application/ thread must be assigned to one of the hardware contexts (strands). We call this last scheduling step the Thread to Strand Binding or TSB. In this paper, we show that the TSB impact on the performance of processors with several levels of shared resources is high. We measure a variation of up to 59% between different TSBs of real multithreaded network applications running on the UltraSPARC T2 processor which has three levels of resource sharing. In our view, this problem is going to be more acute in future multithreaded architectures comprising more cores, more contexts per core, and more levels of resource sharing. We propose a resource-sharing aware TSB algorithm (TSBSched) that significantly facilitates the problem of thread to strand binding for software-pipelined applications, representative ofmultithreaded network applications. Our systematic approach encapsulates both, the characteristics of multithreaded processors under the study and the structure of the software pipelined applications. Once calibrated for a given processor architecture, our proposal does not require hardware knowledge on the side of the programmer, nor extensive profiling of the application. We validate our algorithm on the UltraSPARC T2 processor running a set of real multithreaded network applications on which we report improvements of up to 46% compared to the current state-of-the-art dynamic schedulers.
dc.format.extent11 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshProcess scheduling
dc.subject.lcshSimultaneous multithreading
dc.subject.lcshCMT
dc.subject.lcshUltraSPARC T2
dc.titleThread to strand binding of parallel network applications in massive multi-threaded systems
dc.typeArticle
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
drac.iddocument2750023
dc.description.versionPostprint (published version)
upcommons.citation.authorRadojkovic, P.; Cakarevic, V.; Verdu, J.; Pajuelo, A.; Cazorla, F.; Nemirovsky, M.; Valero, M.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameACM SIGPLAN notices
upcommons.citation.volume45
upcommons.citation.number5
upcommons.citation.startingPage191
upcommons.citation.endingPage201


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder