Implementing kilo-instruction multiprocessors
Document typeExternal research report
Rights accessOpen Access
Multiprocessors are coming into wide-spread use in many application areas, yet there are a number of challenges to achieving a good tradeoff between complexity and performance. For example, while implementing memory coherence and consistency is essential for correctness, efficient implementation of critical sections and synchronization points is desirable for performance. The multi-checkpointing mechanisms of Kilo-Instruction Processors can be leveraged to achieve good complexity-effective multiprocessor designs. We describe how to implement a Kilo-Instruction Multiprocessor that transparently, i.e. without any software support, uses transaction-based memory updates. Our model not only simplifies memory coherence and consistency hardware, but at the same time, it provides the potential for implementing high performance speculative mechanisms for commonly occurring synchronization constructs. Comments: This report is an improved version of the report 'Solving Multiprocessor Drawbacks with Kilo-Instruction Processors'.
CitationVallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J., Valero, M. "Implementing kilo-instruction multiprocessors". 2005.
Is part ofUPC-DAC-RR-CAP-2005-19