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dc.contributor.authorVallejo, Enrique
dc.contributor.authorGalluzzi, Marco
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorVallejo, Fernando
dc.contributor.authorBeivide Palacio, Ramon
dc.contributor.authorStenström, Per
dc.contributor.authorSmith, James E.
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-07-20T10:10:11Z
dc.date.available2017-07-20T10:10:11Z
dc.date.issued2005
dc.identifier.citationVallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J., Valero, M. "Solving multiprocessor drawbacks with kilo-instruction processors". 2005.
dc.identifier.urihttp://hdl.handle.net/2117/106643
dc.description.abstractNowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is essential for correctness the way to solve processor stalls due to critical sections and synchronization points is desirable for performance. And none of these drawbacks has a straightforward solution. We show in our paper how the multi-checkpointing mechanism of the Kilo-Instruction Processors can be correctly leveraged in order to achieve a good complexity-effective multiprocessor design. Specifically, we describe a Kilo-Instruction Multiprocessor that transparently, i.e. without any software support, uses transaction-based memory updates. Our model simplifies the coherence and consistency hardware and gives the potential for easily applying different desirable speculative mechanisms to enhance performance when facing some synchronization constructs of current parallel applications.
dc.format.extent17 p.
dc.language.isoeng
dc.relation.ispartofseriesUPC-DAC-RR-CAP-2005-14
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.otherCMP
dc.subject.otherKilo-Instruction
dc.subject.otherROB
dc.subject.otherCheckpoint
dc.subject.otherShared Memory
dc.subject.otherTransactions
dc.titleSolving multiprocessor drawbacks with kilo-instruction processors
dc.typeExternal research report
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
drac.iddocument21185720
dc.description.versionPostprint (published version)
upcommons.citation.authorVallejo, E.; Galluzzi, M.; Cristal, A.; Vallejo, F.; Beivide, R.; Stenström, P.; Smith, J.; Valero, M.
upcommons.citation.publishedtrue


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