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Solving multiprocessor drawbacks with kilo-instruction processors
dc.contributor.author | Vallejo, Enrique |
dc.contributor.author | Galluzzi, Marco |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Vallejo, Fernando |
dc.contributor.author | Beivide Palacio, Ramon |
dc.contributor.author | Stenström, Per |
dc.contributor.author | Smith, James E. |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-07-20T10:10:11Z |
dc.date.available | 2017-07-20T10:10:11Z |
dc.date.issued | 2005 |
dc.identifier.citation | Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J., Valero, M. "Solving multiprocessor drawbacks with kilo-instruction processors". 2005. |
dc.identifier.uri | http://hdl.handle.net/2117/106643 |
dc.description.abstract | Nowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is essential for correctness the way to solve processor stalls due to critical sections and synchronization points is desirable for performance. And none of these drawbacks has a straightforward solution. We show in our paper how the multi-checkpointing mechanism of the Kilo-Instruction Processors can be correctly leveraged in order to achieve a good complexity-effective multiprocessor design. Specifically, we describe a Kilo-Instruction Multiprocessor that transparently, i.e. without any software support, uses transaction-based memory updates. Our model simplifies the coherence and consistency hardware and gives the potential for easily applying different desirable speculative mechanisms to enhance performance when facing some synchronization constructs of current parallel applications. |
dc.format.extent | 17 p. |
dc.language.iso | eng |
dc.relation.ispartofseries | UPC-DAC-RR-CAP-2005-14 |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Multiprocessors |
dc.subject.other | CMP |
dc.subject.other | Kilo-Instruction |
dc.subject.other | ROB |
dc.subject.other | Checkpoint |
dc.subject.other | Shared Memory |
dc.subject.other | Transactions |
dc.title | Solving multiprocessor drawbacks with kilo-instruction processors |
dc.type | External research report |
dc.subject.lemac | Multiprocessadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.rights.access | Open Access |
local.identifier.drac | 21185720 |
dc.description.version | Postprint (published version) |
local.citation.author | Vallejo, E.; Galluzzi, M.; Cristal, A.; Vallejo, F.; Beivide, R.; Stenström, P.; Smith, J.; Valero, M. |
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