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dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorPeirón Guardia, Montse
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-07-20T07:12:42Z
dc.date.available2017-07-20T07:12:42Z
dc.date.issued1993
dc.identifier.citationValero, M., Peirón, M., Ayguadé, E. Access to streams in multiprocessor systems. A: Euromicro Workshop on Parallel and Distributed Processing. "Euromicro Workshop on Parallel and Distributed Processing: proceedings". Gran Canaria: Institute of Electrical and Electronics Engineers (IEEE), 1993, p. 310-316.
dc.identifier.isbn0-8186-3610-6
dc.identifier.urihttp://hdl.handle.net/2117/106627
dc.description.abstractWhen accessing streams in vector multiprocessor machines, degradation in the interconnection network and conflicts in the memory modules are the factors that reduce the efficiency of the system. In this paper, we present a synchronous access mechanism that allows conflict-free access to streams in a SIMD vector multiprocessor system. Each processor accesses the corresponding elements out of order, in such a way that in each cycle the requested elements do not collide in the interconnection network. Moreover, memory modules are accessed so that conflicts are avoided. The use of the proposed mechanism in present-day architectures would allow conflict-free access to streams with the most common strides that appear in real applications. The additional hardware is described and is shown to be of a similar complexity as that required for access in order.
dc.format.extent7 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.lcshComputer networks
dc.subject.otherMultiprocessor interconnection networks
dc.subject.otherVector processor systems
dc.titleAccess to streams in multiprocessor systems
dc.typeConference report
dc.subject.lemacMultiprocessadors
dc.subject.lemacOrdinadors, Xarxes d'
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/EMPDP.1993.336387
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/336387/
dc.rights.accessOpen Access
drac.iddocument21185420
dc.description.versionPostprint (published version)
upcommons.citation.authorValero, M., Peirón, M., Ayguadé, E.
upcommons.citation.contributorEuromicro Workshop on Parallel and Distributed Processing
upcommons.citation.pubplaceGran Canaria
upcommons.citation.publishedtrue
upcommons.citation.publicationNameEuromicro Workshop on Parallel and Distributed Processing: proceedings
upcommons.citation.startingPage310
upcommons.citation.endingPage316


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