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Analysis and simulation of multiplexed single-bus networks with and without buffering
dc.contributor.author | Llaberia Griñó, José M. |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Herrada Lillo, Enrique |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Facultat d'Informàtica de Barcelona |
dc.date.accessioned | 2017-07-06T11:52:08Z |
dc.date.available | 2017-07-06T11:52:08Z |
dc.date.issued | 1985 |
dc.identifier.citation | Llaberia, J., Valero, M., Herrada, E., Labarta, J. Analysis and simulation of multiplexed single-bus networks with and without buffering. A: International Symposium on Computer Architecture. "ISCA '85: proceedings of the 12th Annual International Symposium on Computer Architecture". Boston, Massachusetts: Institute of Electrical and Electronics Engineers (IEEE), 1985, p. 414-421. |
dc.identifier.isbn | 0-8186-0634-7 |
dc.identifier.uri | http://hdl.handle.net/2117/106203 |
dc.description.abstract | Performance issues of a single-bus interconnection network for multiprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. Comparisons with equivalent crossbar systems are provided. It is shown how crossbar EBW values can be reached and exceeded when appropriate operation parameters are chosen in a multiplexed single-bus system. Another architectural feature is considered, concerning the utilization of buffers at the memory modules. With the buffering scheme, memory interference can be reduced so that the system performance is practically improved. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Computer networks -- Design and construction |
dc.subject.lcsh | Multiprocessors |
dc.subject.other | Computer networks |
dc.subject.other | Digital simulation |
dc.subject.other | Multiprocessing systems |
dc.subject.other | Performance evaluation |
dc.title | Analysis and simulation of multiplexed single-bus networks with and without buffering |
dc.type | Conference report |
dc.subject.lemac | Ordinadors, Xarxes d' -- Disseny i construcció |
dc.subject.lemac | Multiprocessadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1145/327070.327374 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://dl.acm.org/citation.cfm?id=327374&CFID=782406673&CFTOKEN=35610963 |
dc.rights.access | Open Access |
local.identifier.drac | 21146736 |
dc.description.version | Postprint (published version) |
local.citation.author | Llaberia, J.; Valero, M.; Herrada, E.; Labarta, J. |
local.citation.contributor | International Symposium on Computer Architecture |
local.citation.pubplace | Boston, Massachusetts |
local.citation.publicationName | ISCA '85: proceedings of the 12th Annual International Symposium on Computer Architecture |
local.citation.startingPage | 414 |
local.citation.endingPage | 421 |