Analysis and simulation of multiplexed single-bus networks with and without buffering
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Performance issues of a single-bus interconnection network for multiprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. Comparisons with equivalent crossbar systems are provided. It is shown how crossbar EBW values can be reached and exceeded when appropriate operation parameters are chosen in a multiplexed single-bus system. Another architectural feature is considered, concerning the utilization of buffers at the memory modules. With the buffering scheme, memory interference can be reduced so that the system performance is practically improved.
CitationLlaberia, J., Valero, M., Herrada, E., Labarta, J. Analysis and simulation of multiplexed single-bus networks with and without buffering. A: International Symposium on Computer Architecture. "ISCA '85: proceedings of the 12th Annual International Symposium on Computer Architecture". Boston, Massachusetts: Institute of Electrical and Electronics Engineers (IEEE), 1985, p. 414-421.
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder