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dc.contributor.authorAzevedo, Arnaldo
dc.contributor.authorJuurlink, Ben
dc.contributor.authorMeenderinck, Cor
dc.contributor.authorTerechko, Andrei
dc.contributor.authorHoogerbrugge, Jan
dc.contributor.authorÁlvarez Mesa, Mauricio
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-07-06T10:22:22Z
dc.date.available2017-07-06T10:22:22Z
dc.date.issued2011
dc.identifier.citationAzevedo, A., Juurlink, B., Meenderinck, C., Terechko, A., Hoogerbrugge, J., Álvarez, M., Ramírez, A., Valero, M. A highly scalable parallel implementation of H.264. "Transactions on HiPEAC", 2011, vol. 4, p. 111-134.
dc.identifier.issn1864-306X
dc.identifier.urihttp://hdl.handle.net/2117/106197
dc.description.abstractDeveloping parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation of H.264 that scales to a large number of cores. The algorithm exploits the fact that independent macroblocks (MBs) can be processed in parallel, but whereas a previous approach exploits only intra-frame MB-level parallelism, our algorithm exploits intra-frame as well as inter-frame MB-level parallelism. It is based on the observation that inter-frame dependencies have a limited spatial range. The algorithm has been implemented on a many-core architecture consisting of NXP TriMedia TM3270 embedded processors. This required to develop a subscription mechanism, where MBs are subscribed to the kick-off lists associated with the reference MBs. Extensive simulation results show that the implementation scales very well, achieving a speedup of more than 54 on a 64-core processor, in which case the previous approach achieves a speedup of only 23. Potential drawbacks of the 3D-Wave strategy are that the memory requirements increase since there can be many frames in flight, and that the frame latency might increase. Scheduling policies to address these drawbacks are also presented. The results show that these policies combat memory and latency issues with a negligible effect on the performance scalability. Results analyzing the impact of the memory latency, L1 cache size, and the synchronization and thread management overhead are also presented. Finally, we present performance requirements for entropy (CABAC) decoding. This work was performed while the fourth author was with NXP Semiconductors.
dc.format.extent24 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshEmbedded computer systems
dc.subject.lcshMultiprocessors
dc.subject.otherEmbedded systems
dc.subject.otherEntropy
dc.subject.otherMultiprocessing systems
dc.subject.otherMultithreading
dc.subject.otherParallel architectures
dc.subject.otherProcessor scheduling
dc.subject.otherVideo coding
dc.titleA highly scalable parallel implementation of H.264
dc.typeArticle
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacOrdinadors immersos, Sistemes d'
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1007/978-3-642-24568-8_6
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://link.springer.com/chapter/10.1007/978-3-642-24568-8_6
dc.rights.accessOpen Access
local.identifier.drac2574057
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
local.citation.authorAzevedo, A.; Juurlink, B.; Meenderinck, C.; Terechko, A.; Hoogerbrugge, J.; Álvarez, M.; Ramírez, A.; Valero, M.
local.citation.publicationNameTransactions on HiPEAC
local.citation.volume4
local.citation.startingPage111
local.citation.endingPage134


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