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DIA: A complexity-effective decoding architecture
dc.contributor.author | Santana Jaria, Oliverio J. |
dc.contributor.author | Falcón Samper, Ayose Jesus |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-07-06T07:46:09Z |
dc.date.available | 2017-07-06T07:46:09Z |
dc.date.issued | 2009-04 |
dc.identifier.citation | Santana, O., Falcón, A., Ramírez, A., Valero, M. DIA: A complexity-effective decoding architecture. "IEEE transactions on computers", Abril 2009, vol. 58, núm. 4, p. 448-462. |
dc.identifier.issn | 0018-9340 |
dc.identifier.uri | http://hdl.handle.net/2117/106190 |
dc.description.abstract | Fast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware buffer. Fetching already decoded instructions avoids the need for decoding them again, improving processor performance. However, introducing such special--purpose storage in the processor design involves an important increase in the fetch architecture complexity. In this paper, we propose a novel decoding architecture that reduces the fetch engine implementation cost. Instead of using a special-purpose hardware buffer, our proposal stores frequently decoded instructions in the memory hierarchy. The address where the decoded instructions are stored is kept in the branch prediction mechanism, enabling it to guide our decoding architecture. This makes it possible for the processor front end to fetch already decoded instructions from the memory instead of the original nondecoded instructions. Our results show that using our decoding architecture, a state-of-the-art superscalar processor achieves competitive performance improvements, while requiring less chip area and energy consumption in the fetch architecture than a hardware code caching mechanism. |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Microprocessors |
dc.subject.lcsh | Logic design |
dc.subject.other | Superscalar processor design |
dc.subject.other | CISC instruction decoding |
dc.subject.other | Variable-length ISA |
dc.subject.other | Branch predictor |
dc.subject.other | Code caching |
dc.title | DIA: A complexity-effective decoding architecture |
dc.type | Article |
dc.subject.lemac | Microprocessadors |
dc.subject.lemac | Estructura lògica |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/TC.2008.170 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/4624251/ |
dc.rights.access | Open Access |
local.identifier.drac | 655025 |
dc.description.version | Postprint (published version) |
local.citation.author | Santana, O.; Falcón, A.; Ramírez, A.; Valero, M. |
local.citation.publicationName | IEEE transactions on computers |
local.citation.volume | 58 |
local.citation.number | 4 |
local.citation.startingPage | 448 |
local.citation.endingPage | 462 |
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