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A DRAM/SRAM memory scheme for fast packet buffers
dc.contributor.author | García Vidal, Jorge |
dc.contributor.author | March, Maribel |
dc.contributor.author | Cerdà Alabern, Llorenç |
dc.contributor.author | Corbal San Adrián, Jesús |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-06-30T07:28:34Z |
dc.date.available | 2017-06-30T07:28:34Z |
dc.date.issued | 2006-05 |
dc.identifier.citation | García, J., March, M., Cerdà, L., Corbal, J., Valero, M. A DRAM/SRAM memory scheme for fast packet buffers. "IEEE transactions on computers", Maig 2006, vol. 55, núm. 5, p. 588-602. |
dc.identifier.issn | 0018-9340 |
dc.identifier.uri | http://hdl.handle.net/2117/106017 |
dc.description.abstract | We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps. |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
dc.subject.lcsh | Routing (Computer network management) |
dc.subject.other | Router architecture |
dc.subject.other | Packet buffers |
dc.subject.other | High-performance memory systems |
dc.subject.other | Storage schemes |
dc.title | A DRAM/SRAM memory scheme for fast packet buffers |
dc.type | Article |
dc.subject.lemac | Encaminadors (Xarxes d'ordinadors) |
dc.contributor.group | Universitat Politècnica de Catalunya. CNDS - Xarxes de Computadors i Sistemes Distribuïts |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/TC.2006.63 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1613839/ |
dc.rights.access | Open Access |
local.identifier.drac | 654903 |
dc.description.version | Postprint (published version) |
local.citation.author | García, J.; March, M.; Cerdà, L.; Corbal, J.; Valero, M. |
local.citation.publicationName | IEEE transactions on computers |
local.citation.volume | 55 |
local.citation.number | 5 |
local.citation.startingPage | 588 |
local.citation.endingPage | 602 |
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