Show simple item record

dc.contributor.authorSantana Jaria, Oliverio J.
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-06-30T07:15:13Z
dc.date.available2017-06-30T07:15:13Z
dc.date.issued2005-03
dc.identifier.citationSantana, O., Ramírez , A., Valero, M. "Techniques for enlarging instruction streams". 2005.
dc.identifier.urihttp://hdl.handle.net/2117/106016
dc.description.abstractThis work presents several techniques for enlarging instruction streams. We call stream to a sequence of instructions from the target of a taken branch to the next taken branch, potentially containing multiple basic blocks. The long size of instruction streams makes it possible for a fetch engine based on streams to provide high fetch bandwidth, which leads to obtaining performance results comparable to a trace cache. The long size of streams also enables the next stream predictor to tolerate the prediction table access latency. Therefore, enlarging instruction streams will improve the behavior of a fetch engine based on streams. We provide a comprehensive analysis of dynamic instruction streams, showing that focusing on particular kinds of stream is not a good strategy due to Amdahl's law. Consequently, we propose the multiple stream predictor, a novel mechanism that deals with all kinds of streams by combining single streams into long virtual streams. We show that our multiple stream predictor is able to tolerate the prediction access latency without requiring the complexity caused by additional hardware mechanisms like prediction overriding.
dc.format.extent35 p.
dc.language.isoeng
dc.relation.ispartofseriesUPC-DAC-RR-CAP-2005-5
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.lcshParallel processing (Electronic computers)
dc.titleTechniques for enlarging instruction streams
dc.typeExternal research report
dc.subject.lemacMultiprocessadors
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
drac.iddocument21126067
dc.description.versionPostprint (published version)
upcommons.citation.authorSantana, O., Ramírez , A., Valero, M.
upcommons.citation.publishedtrue


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder