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dc.contributor.authorPericàs Gleim, Miquel
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorCazorla, Francisco
dc.contributor.authorGonzález García, Rubén
dc.contributor.authorVeidenbaum, Alexander V
dc.contributor.authorJiménez, Daniel A.
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationPericàs, M., Cristal, A., Cazorla, F., González, R., Veidenbaum, A.V., Jiménez, D. A., Valero, M. A two level load/store queue based on execution locality. A: International Symposium on Computer Arquitecture. "ISCA 2008 Proceedings: 35th International Symposium on Computer Architecture: 21-25 June 2008, Beijing, China". Beijing: Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 25-36.
dc.description.abstractMulticore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential components of applications. To overcome this limitation it is necessary to design processors with many lower–performance cores for TLP and some high-performance cores designed to execute sequential algorithms. Such cores will need to address the memory-wall by implementing kilo-instruction windows. Large window processors require large Load/Store Queues that would be too slow if implemented using current CAMbased designs. This paper proposes an Epoch-based Load Store Queue (ELSQ), a new design based on Execution Locality. It is integrated into a large-window processor that has a fast, out-of-order core operating only on L1/L2 cache hits and N slower cores that process L2 misses and their dependent instructions. The large LSQ is coupled with the slow cores and is partitioned into N small and local LSQs, one per core. We evaluate ELSQ in a large-window environment, finding that it enables high performance at low power. By exploiting locality among loads and stores, ELSQ outperforms even an idealized central LSQ when implemented on top of a decoupled processor design.
dc.format.extent12 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCache memory
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherParallel processing
dc.subject.otherCache storage
dc.titleA two level load/store queue based on execution locality
dc.typeConference report
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
upcommons.citation.authorPericàs, M., Cristal, A., Cazorla, F., González, R., Veidenbaum, A.V., Jiménez, D. A., Valero, M.
upcommons.citation.contributorInternational Symposium on Computer Arquitecture
upcommons.citation.publicationNameISCA 2008 Proceedings: 35th International Symposium on Computer Architecture: 21-25 June 2008, Beijing, China

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