| dc.contributor.author | Navarro Guerrero, Juan José |
| dc.contributor.author | Llaberia Griñó, José M. |
| dc.contributor.author | Valero Cortés, Mateo |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2017-06-22T09:59:25Z |
| dc.date.available | 2017-06-22T09:59:25Z |
| dc.date.issued | 1986 |
| dc.identifier.citation | Navarro, J., Llaberia, J., Valero, M. Computing size-independent matrix problems on systolic array processors. A: International Symposium on Computer Architecture. "Proceedings of the 13th Annual International Symposium on Computer Architecture". Tokyo: Institute of Electrical and Electronics Engineers (IEEE), 1986, p. 271-278. |
| dc.identifier.isbn | 0-8186-0719-X |
| dc.identifier.uri | http://hdl.handle.net/2117/105729 |
| dc.description.abstract | A methodology to transform dense to band matrices is presented in this paper. This transformation, is accomplished by triangular blocks partitioning, and allows the implementation of solutions to problems with any given size, by means of contraflow systolic arrays, originally proposed by H.T. Kung. Matrix-vector and matrix-matrix multiplications are the operations considered here.The proposed transformations allow the optimal utilization of processing elements (PEs) of the systolic array when dense matrix are operated. Every computation is made inside the array by using adequate feedback. The feedback delay time depends only on the systolic array size. |
| dc.format.extent | 8 p. |
| dc.language.iso | eng |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Systolic array circuits |
| dc.subject.other | Matrices |
| dc.subject.other | Triangular blocks partitioning |
| dc.subject.other | Systolic arrays |
| dc.title | Computing size-independent matrix problems on systolic array processors |
| dc.type | Conference report |
| dc.subject.lemac | Processadors de matrius (arrays) |
| dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| dc.identifier.doi | 10.1145/17356.17388 |
| dc.description.peerreviewed | Peer Reviewed |
| dc.relation.publisherversion | http://dl.acm.org/citation.cfm?id=17388 |
| dc.rights.access | Open Access |
| drac.iddocument | 21110492 |
| dc.description.version | Postprint (published version) |
| upcommons.citation.author | Navarro, J., Llaberia, J., Valero, M. |
| upcommons.citation.contributor | International Symposium on Computer Architecture |
| upcommons.citation.pubplace | Tokyo |
| upcommons.citation.published | true |
| upcommons.citation.publicationName | Proceedings of the 13th Annual International Symposium on Computer Architecture |
| upcommons.citation.startingPage | 271 |
| upcommons.citation.endingPage | 278 |
