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dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.authorValero García, Miguel
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationGonzález, A., Valero-García, M. The Xor embedding: An embedding of hypercubes onto rings and toruses. A: International Conference on Application-Specific Array Processors. "International Conference on Application-Specific Array Processors, 1993: proceedings". Vecine: Institute of Electrical and Electronics Engineers (IEEE), 1993, p. 15-28.
dc.description.abstractMany parallel algorithms use hypercubes as the communication topology among processes, which make them suitable to be executed on a hypercube multicomputer. In this way the communication cost is kept to a minimum since processes can be allocated to processors in such a way that only communication between neighbor processors is required. However, the scalability of hypercube multicomputer is constrained by the fact that the interconnection cost per node increases with the total number of nodes. From the point of view of scalability, meshes and toruses are a more interesting class of interconnection topologies. In this paper the authors propose an embedding of hypercubes onto toruses of any given dimension, incuding one-dimensional toruses which are also called rings. They also prove that the embedding is optimal in the sense that it minimizes the execution time on a ring of a class of parallel algorithms frequently found in real applications, such as FFT and some class of sorting algorithms.
dc.format.extent14 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshParallel algorithms
dc.subject.otherHypercube networks
dc.subject.otherFast Fourier transforms
dc.subject.otherParallel architectures
dc.titleThe Xor embedding: An embedding of hypercubes onto rings and toruses
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacAlgorismes paral·lels
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
local.citation.authorGonzález, A.; Valero-García, M
local.citation.contributorInternational Conference on Application-Specific Array Processors
local.citation.publicationNameInternational Conference on Application-Specific Array Processors, 1993: proceedings

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