Trace-level speculative multithreaded architecture
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
This paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectively. The architecture presents two main benefits: (a) no significant penalties are introduced in the presence of a misspeculation and (b) any type of trace predictor can work together with this proposal. In this way, aggressive trace predictors can be incorporated since misspeculations do not introduce significant penalties. We describe in detail TSMA (trace-level speculative multithreaded architecture) and present initial results to show the benefits of this proposal. We show how simple trace predictors achieve significant speed-up in the majority of cases. Results of a simple trace speculation mechanism show an average speed-up of 16%.
CitacióMolina, C., González, A., Tubella, J. Trace-level speculative multithreaded architecture. A: IEEE International Conference on Computer Design: VLSI in Computers and Processors. "2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors: September 16-18, 2002 Freiburg, Germany: proceedings". Freiburg: Institute of Electrical and Electronics Engineers (IEEE), 2002, p. 402-407.
Versió de l'editorhttp://ieeexplore.ieee.org.recursos.biblioteca.upc.edu/document/1106802/