Mostra el registre d'ítem simple
Power-aware load balancing of large scale MPI applications
dc.contributor.author | Etinski, Maja |
dc.contributor.author | Corbalán González, Julita |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Veidenbaum, Alex |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-06-01T09:17:56Z |
dc.date.available | 2017-06-01T09:17:56Z |
dc.date.issued | 2009 |
dc.identifier.citation | Etinski, M., Corbalán, J., Labarta, J., Valero, M., Veidenbaum, A. Power-aware load balancing of large scale MPI applications. A: IEEE International Parallel and Distributed Processing Symposium. "Program 23rd IEEE International Parallel & Distributed Processing Symposium: May 25-29, 2009". Roma: Institute of Electrical and Electronics Engineers (IEEE), 2009, p. 1-8. |
dc.identifier.isbn | 978-1-4244-3751-1 |
dc.identifier.uri | http://hdl.handle.net/2117/105097 |
dc.description.abstract | Power consumption is a very important issue for HPC community, both at the level of one application or at the level of whole workload. Load imbalance of a MPI application can be exploited to save CPU energy without penalizing the execution time. An application is load imbalanced when some nodes are assigned more computation than others. The nodes with less computation can be run at lower frequency since otherwise they have to wait for the nodes with more computation blocked in MPI calls. A technique that can be used to reduce the speed is Dynamic Voltage Frequency Scaling (DVFS). Dynamic power dissipation is proportional to the product of the frequency and the square of the supply voltage, while static power is proportional to the supply voltage. Thus decreasing voltage and/or frequency results in power reduction. Furthermore, over-clocking can be applied in some CPUs to reduce overall execution time. This paper investigates the impact of using different gear sets , over-clocking, and application and platform propreties to reduce CPU power. A new algorithm applying DVFS and CPU over-clocking is proposed that reduces execution time while achieving power savings comparable to prior work. The results show that it is possible to save up to 60% of CPU energy in applications with high load imbalance. Our results show that six gear sets achieve, on average, results close to the continuous frequency set that has been used as a baseline. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | High performance computing -- Energy conservation |
dc.subject.other | Resource allocation |
dc.subject.other | Application program interfaces |
dc.subject.other | Message passing |
dc.subject.other | Power aware computing |
dc.subject.other | Power consumption |
dc.title | Power-aware load balancing of large scale MPI applications |
dc.type | Conference report |
dc.subject.lemac | Càlcul intensiu (Informàtica) -- Estalvi d'energia |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/IPDPS.2009.5160973 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/5160973/ |
dc.rights.access | Open Access |
local.identifier.drac | 11152372 |
dc.description.version | Postprint (published version) |
local.citation.author | Etinski, M.; Corbalán, J.; Labarta, J.; Valero, M.; Veidenbaum, A. |
local.citation.contributor | IEEE International Parallel and Distributed Processing Symposium |
local.citation.pubplace | Roma |
local.citation.publicationName | Program 23rd IEEE International Parallel & Distributed Processing Symposium: May 25-29, 2009 |
local.citation.startingPage | 1 |
local.citation.endingPage | 8 |