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dc.contributor.authorEtinski, Maja
dc.contributor.authorCorbalán González, Julita
dc.contributor.authorLabarta Mancho, Jesús José
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorVeidenbaum, Alex
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-06-01T09:17:56Z
dc.date.available2017-06-01T09:17:56Z
dc.date.issued2009
dc.identifier.citationEtinski, M., Corbalán, J., Labarta, J., Valero, M., Veidenbaum, A. Power-aware load balancing of large scale MPI applications. A: IEEE International Parallel and Distributed Processing Symposium. "Program 23rd IEEE International Parallel & Distributed Processing Symposium: May 25-29, 2009". Roma: Institute of Electrical and Electronics Engineers (IEEE), 2009, p. 1-8.
dc.identifier.isbn978-1-4244-3751-1
dc.identifier.urihttp://hdl.handle.net/2117/105097
dc.description.abstractPower consumption is a very important issue for HPC community, both at the level of one application or at the level of whole workload. Load imbalance of a MPI application can be exploited to save CPU energy without penalizing the execution time. An application is load imbalanced when some nodes are assigned more computation than others. The nodes with less computation can be run at lower frequency since otherwise they have to wait for the nodes with more computation blocked in MPI calls. A technique that can be used to reduce the speed is Dynamic Voltage Frequency Scaling (DVFS). Dynamic power dissipation is proportional to the product of the frequency and the square of the supply voltage, while static power is proportional to the supply voltage. Thus decreasing voltage and/or frequency results in power reduction. Furthermore, over-clocking can be applied in some CPUs to reduce overall execution time. This paper investigates the impact of using different gear sets , over-clocking, and application and platform propreties to reduce CPU power. A new algorithm applying DVFS and CPU over-clocking is proposed that reduces execution time while achieving power savings comparable to prior work. The results show that it is possible to save up to 60% of CPU energy in applications with high load imbalance. Our results show that six gear sets achieve, on average, results close to the continuous frequency set that has been used as a baseline.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHigh performance computing -- Energy conservation
dc.subject.otherResource allocation
dc.subject.otherApplication program interfaces
dc.subject.otherMessage passing
dc.subject.otherPower aware computing
dc.subject.otherPower consumption
dc.titlePower-aware load balancing of large scale MPI applications
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica) -- Estalvi d'energia
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/IPDPS.2009.5160973
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/5160973/
dc.rights.accessOpen Access
local.identifier.drac11152372
dc.description.versionPostprint (published version)
local.citation.authorEtinski, M.; Corbalán, J.; Labarta, J.; Valero, M.; Veidenbaum, A.
local.citation.contributorIEEE International Parallel and Distributed Processing Symposium
local.citation.pubplaceRoma
local.citation.publicationNameProgram 23rd IEEE International Parallel & Distributed Processing Symposium: May 25-29, 2009
local.citation.startingPage1
local.citation.endingPage8


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