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A new pointer-based instruction queue design and its power-performance evaluation
dc.contributor.author | Ramírez, Marco A |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Veidenbaum, Alexander V |
dc.contributor.author | Villa, Luis |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-05-18T10:32:20Z |
dc.date.available | 2017-05-18T10:32:20Z |
dc.date.issued | 2005 |
dc.identifier.citation | Ramírez, M., Cristal, A., Veidenbaum, A.V., Villa, L., Valero, M. A new pointer-based instruction queue design and its power-performance evaluation. A: IEEE International Conference on Computer Design. "2005 International Conference on Computer Design: 02-05 October 2005 San Jose, California: proceedings". San Jose, California: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 647-653. |
dc.identifier.isbn | 0-7695-2451-6 |
dc.identifier.uri | http://hdl.handle.net/2117/104598 |
dc.description.abstract | Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointer-based design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption. |
dc.format.extent | 7 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Microprocessors -- Energy consumption |
dc.subject.other | Low power |
dc.subject.other | Instruction wakeup |
dc.subject.other | Issue queue |
dc.subject.other | Out-of-order processors |
dc.subject.other | CAM |
dc.title | A new pointer-based instruction queue design and its power-performance evaluation |
dc.type | Conference report |
dc.subject.lemac | Microprocessadors -- Consum d'energia |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/ICCD.2005.12 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1524220/ |
dc.rights.access | Open Access |
local.identifier.drac | 2421111 |
dc.description.version | Postprint (published version) |
local.citation.author | Ramírez, M.; Cristal, A.; Veidenbaum, A.V.; Villa, L.; Valero, M. |
local.citation.contributor | IEEE International Conference on Computer Design |
local.citation.pubplace | San Jose, California |
local.citation.publicationName | 2005 International Conference on Computer Design: 02-05 October 2005 San Jose, California: proceedings |
local.citation.startingPage | 647 |
local.citation.endingPage | 653 |